Integrated circuits (ICs) are used in many portable electronic products, such as cell phones, portable computers, and voice recorders as well as in many larger electronic systems, such as cars, planes, industrial control systems, etc. The continuing trend within the semiconductor industry is to form these integrated circuits on semiconductor substrates that have increasingly higher device densities and smaller device feature size (i.e., smaller critical dimensions). Unfortunately, this continued shrinkage and increased device density for integrated circuits brings with it new problems. One such problem is the variation in deposited film thickness as a function of feature geometry.
For example, one potential problem is when selective epitaxy processes deposit epilayers of different thicknesses at different regions of an IC. Selective epitaxy involves the selective deposition of epilayers over mono-crystalline regions without the simultaneous deposition of amorphous or polycrystalline layers over dielectric material and/or amorphous regions. The mono-crystalline regions where epilayers are formed thereover are referred to as seed windows. Selective epitaxy may be used in the formation of semiconductor device features such as elevated source/drain, embedded stress inducing layers, base layers of bipolar transistors and contact plugs.
Variations in epilayer thickness deposited on similar device features of an IC are undesirable as this may lead to a corresponding variation in device characteristics such as subthreshold characteristics, threshold voltage roll-off and drain induced barrier lowering and consequently degraded device yield.
In view of the above, deposition methods that mitigate growth rate variations caused by loading effect are desirable.